Design and Comparison of Wallace Multiplier Based on Symmetric Stacking and High speed counters

Authors

  • B.L. Chandrika Post Graduate Scholar, UTL technologies Ltd, Bengaluru, India
  • Santhosh N S Post Graduate Scholar, UTL technologies Ltd, Bengaluru, India
  • Amaresha S K Assistant Professor, UTL technologies Ltd, Bengaluru, India

DOI:

https://doi.org/10.31695/IJERAT.2018.3271

Keywords:

Stacking circuits, Column compression, High speed counters.

Abstract

High latency and efficient addition of multiple operands is an essential operation in any computational unit. The latency, power efficiency and area of multiplier circuits is of critical importance in the performance of processors. Multiplier circuits are an essential part of an arithmetic logic unit, or a digital signal processor system for performing filtering and convolution. The binary multiplication of integers or fixed-point numbers results in partial products that must be added to produce the final product. The addition of these partial products dominates the latency and power consumption of the multiplier. In order to combine the partial products efficiently, column compression is commonly used. Many methods have been presented to optimize the performance of the partial product summation previously. To achieve higher efficiency, more number of bits need to be reduced at a time. For this, the column compression techniques can be used. By using this, the critical path delay can be reduced and also the latency of the multiplier. When higher compression unit is used the energy of the multiplier is also reduced. In this paper, the column compression techniques are compared. The stacking circuits presented in, show an improvement over algorithmic Wallace multiplier which uses the generic equations for the column compression units. In stacking units, the 7:3 and 6:3 counters are derived from a basic 3-bit stacking circuit reducing usage of XOR gates. This reduces the usage of XOR gates and thus the critical delay. While the algorithmic units use generic equations using the generation and propagation functions of an adder.

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Published

2018-06-05

How to Cite

Design and Comparison of Wallace Multiplier Based on Symmetric Stacking and High speed counters. (2018). International Journal of Engineering Research and Advanced Technology (ijerat) (E-ISSN 2454-6135) DOI: 10.31695 IJERAT, 4(6), 06-15. https://doi.org/10.31695/IJERAT.2018.3271