Approximate Low power, high-performance Adder and Multiplier Design using Error Tolerance Application

Abstract

The small error introduce some effect of application and also wastage area and power of the design but in this proposed design the error tolerance adder introduce in the design not affect design it reduces power, area, delay of the design. The performance improves in this 9x9 Wallace tree multipliers. Proposed multipliers improve the performance of the design reduce leakage power, dynamic power. Compare conventional and proposed multipliers in this paper used 9x9 multipliers, adders. wallace tree multipliers concepts using in this design. The more quality depends on error free design but some application of design depends on error tolerance application improve design speed, performance, time constrain of design. The proposed adder and multiplier design is improved and achieved performance, speed and low delay of design.ETA application using multimedia application, DSP application. The multimedia application and DSP application speed can be increased and performance of design also improved. Design implementation using proposed adder like, HA, FA, CLA, CRA.9x9 Wallace tree multipliers design comparing existing and proposed method design. Proposed design method improves its performance 90% compare to existing method design. The Wallace tree multipliers design  minimize number gates in adder and multipliers design circuits. partial products generation reduces number of step of design and minimize area of design. Partial products get final sum of result. The Wallace tree multipliers technology complexity of the design is reduces. Wallace tree multipliers improve gate level and circuit level design performance. The error tolerances proposed design not get exact simulation result that result variations compare to existing result but proposed design performance, speed increases and area reduces.