Low power 7T SRAM cell optimization with 45nm Technology

Abstract

A new low power SRAM cell introduced that promises improved performance by adding extra circuitry to a 6T-SRAM cell. This new design features a 7T(seven-transistors) cell at 45nm size CMOS technology, aiming to enhance power efficiency, stability, overall performance compared to older designs for low power memory operations. By optimize the size and implementing a novel write circuitry scheme, new (seven transistor) 7T SRAM cell full fill a significant 45% reduction in power consumption during memory operations when compared to the traditional 6T SRAM-based design. Furthermore, through CADENCE simulations, it is shown that this 7T SRAM cell is highly resistant to process variations, highlighting its robustness and reliability in real-world applications.