The Performance of SRAM Cell Topologies with 6 T, 7 T, 8 T And 9 T Technologies at 45 Nm Technology node

Abstract

 Numerous SRAM cell architectures employing 45nm technology were simulated in the Tanner tool used for this inquiry. In every arrangement, variables like read latency, write delay, power read, power write consumption, read static noise margin (RSNM), and write static noise margin (WSNM) were examined. Of all the designs, the 7T SRAM cell stands out for having the lowest power read utilization. Nevertheless, compared to the 6T SRAM cell, the 8T SRAM cell displayed a 44.15% reduction in power write power. The 9T SRAM cell exhibited the lowest write latency of all the cells tested. Among all the simulated devices, the traditional 6T SRAM cell also showed the highest RSNM value. There was discovered the 8T SRAM cell's WSNM.